ISL25700FRUZ-TK【PDF 7/18 页】IC TEMP SWITCH MFET DRVR 10TQFN

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Sheet目录40

3页 4页 5页 6页 [7页]8页 9页 10页 11页

ISL25700

FN6885.0

September 3, 2010

(Note 11)

SCL Falling Edge to SDA

Output Data Valid

SCL falling edge crossing 30% of V

I2C

until SDA exits the 30% to 70% of

I2C

window

900

BUF

(Note 11)

Time the Bus Must be Free

Before the Start of a New

Transmission

SDA crossing 70% of V

I2C

during a

STOP condition, to SDA crossing 70%

of V

I2C

during the following START

condition

1300

LOW

Clock LOW Time

Measured at the 30% of V

I2C

crossing

1300

HIGH

Clock HIGH Time

Measured at the 70% of V

I2C

crossing

600

SU:STA

START Condition Setup Time SCL rising edge to SDA falling edge.

Both crossing 70% of V

I2C

600

HD:STA

START Condition Hold Time

From SDA falling edge crossing 30%

of V

I2C

to SCL falling edge crossing

70% of V

I2C

600

SU:DAT

Input Data Setup Time

From SDA exiting the 30% to 70% of

I2C

window, to SCL rising edge

crossing 30% of V

I2C

100

HD:DAT

Input Data Hold Time

From SCL falling edge crossing 70% of

I2C

to SDA entering the 30% to 70%

of V

I2C

window

SU:STO

STOP Condition Setup Time

From SCL rising edge crossing 70% of

I2C

, to SDA rising edge crossing 30%

of V

I2C

600

Output Data Hold Time

From SCL falling edge crossing 30% of

I2C

, until SDA enters the 30% to

70% of V

I2C

window

SDA and SCL Rise Time

From 30% to 70% of V

I2C

20 +

0.1 * Cb

250

SDA and SCL Fall Time

From 70% to 30% of V

I2C

20 +

0.1 * Cb

250

Capacitive Loading of SDA or SCL Total on-chip and off-chip

400

Rpu

(Note 11)

SDA and SCL Bus Pull-Up

Resistor Off-Chip

Maximum is determined by t

and t

For Cb = 400pF, max is about 2~2.5k?

For Cb = 40pF, max is about 15~20k?/DIV>

k?/DIV>

(Notes

11, 12)

Non-Volatile Write Cycle Time

NOTES:

6. Typical values are for T

= +25癈 and 12V supply voltage.

7. LSB: [VDAC

255

VDAC

]/255. VDAC

255

and VDAC

are the DAC output voltage when DAC register set to FF hex and 00 hex

respectively.

8. DNL = [VDAC

VDAC

i-1

]/LSB-1, for i = 1 to 255. i is the DAC register setting.

9. INL = [VDAC

(i " LSB + VDAC

)]/LSB for i = 1 to 255.

10.

for i = 1 to 255 decimal, T = -40癈 to +125癈, referenced to 40癈.

11. Limits established by characterization and are not production tested.

12. t

is the time from a valid STOP condition at the end of a Write sequence of a I

C serial interface Write operation, to the

end of the self-timed internal non-volatile write cycle. The Busy Polling method can be used to determine the end of the

non-volatile write cycle.

13. Parameters with MIN and/or MAX limits are 100% tested at +25癈, unless otherwise specified. Temperature limits established

by characterization and are not production tested.

14. B

25/85

is a thermistor material specific constant; represents the slope of the Resistance vs. Temperature curve.

Operating Specifications Over the recommended operating conditions unless otherwise specified. Boldface limits

apply over the operating temperature range, -40癈 to +125癈. (Continued)

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

(Note 13)

TYP

(Note 6)

MAX

(Note 13) UNITS

VDAC

( ) VDAC

40癈

(

)

VDAC

40癈

(

)

------------------------------------------------------------------------ -

T 40

(

)癈

--------------------------- -

?/DIV>

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